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ISL6263
Data Sheet June 10, 2010 FN9213.2
5-Bit VID Single-Phase Voltage Regulator for IMVP-6+ Santa Rosa GPU Core
The ISL6263 IC is a Single-Phase Synchronous-Buck PWM voltage regulator featuring Intersil's Robust Ripple Regulator (R3) TechnologyTM. The ISL6263 is an implementation of the Intel(R) Mobile Voltage Positioning (IMVP) protocol for GPU Render Engine core power. Integrated MOSFET drivers, bootstrap diode, and droop amplifier result in lower component cost and smaller implementation area. Intersil's R3 TechnologyTM combines the best features of both fixed-frequency PWM and hysteretic PWM, delivering excellent light-load efficiency and superior load transient response by commanding variable switching frequency during the transitory event. To maximize light load efficiency, the ISL6263 automatically transitions between continuous-conduction-mode (CCM) and discontinuous-conduction-mode (DCM.) During DCM the low-side MOSFET enters diode-emulation-mode (DEM.) DEM is enabled whenever a Render Suspend state has been set on the VID inputs. Optionally, DEM can be enabled for all VID states by setting the FDE pin high. The ISL6263 has an audio filter that can be enabled in any Render Suspend state by pulling the AF_EN pin high. The audio filter prevents the PWM switching frequency from entering the audible spectrum due to extremely light load while in DEM. The Render core voltage can be dynamically programmed from 0.41200V to 1.28750V by the five VID input pins without requiring sequential stepping of the VID states. The ISL6263 uses the same capacitor for the soft-start slew-rate and for the dynamic VID slew-rate by internally connecting the SOFT pin to the appropriate current source. Processor socket Kelvin sensing is accomplished with an integrated unity-gain true differential amplifier.
Features
* Precision single-phase core voltage regulator - 0.5% system accuracy 0C to +100C - Differential remote GPU die voltage sensing - Differential droop voltage sensing * Applications up to 25A * Input voltage range: +5.0V to +25.0V * Programmable PWM frequency: 200kHz to 500kHz * Pre-biased output start-up capability * 5-bit voltage identification input (VID) - 1.28750 to 0.41200V - 25.75mV steps - Sequential or non-sequential VID change on-the-fly * Selectable diode emulation mode - Render Suspend mode only - Render Performance and Render Suspend mode * Selectable audio filter in render suspend mode * Integrated MOSFET drivers and bootstrap diode * Choice of current sensing schemes - Lossless inductor DCR current sensing - Precision resistive current sensing * Overvoltage, undervoltage, and overcurrent protection * Pb-free plus anneal available (RoHS compliant)
Pinout
ISL6263 (32 LD 5x5 QFN) TOP VIEW
PGOOD AF_EN VR_ON I2UA VID4 VID3 VID2 FDE
32 RBIAS SOFT OCSET VW COMP FB VDIFF VSEN 1 2 3 4 5 6 7 8 9 RTN
31
30
29
28
27
26
25 24 23 22 VID1 VID0 PVCC LGATE PGND PHASE UGATE BOOT
GND PAD (BOTTOM)
21 20 19 18 17
10 DROOP
11 DFB
12 VO
13 VSUM
14 VIN
15 VSS
16 VDD
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2010. All Rights Reserved. R3 TechnologyTM is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
ISL6263 Ordering Information
PART NUMBER (Notes 2, 3) ISL6263CRZ ISL6263CRZ-T (Note 1) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6263. For more information on MSL please see techbrief TB363. PART MARKING ISL 6263CRZ ISL 6263CRZ TEMP RANGE (C) -10 to 100 -10 to 100 PACKAGE (Pb-Free) 32 Ld 5x5 QFN 32 Ld 5x5 QFN Tape & Reel PKG. DWG. # L32.5x5 L32.5x5
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FN9213.2 June 10, 2010
Block Diagram
I2UA VDD VR_ON PGOOD BOOT PWM CONTROL DIODE EMULATION AUDIBLE FREQUENCY FILTER SEVERE OVERVOLTAGE SOFT CROWBAR CONTROL PHASE SHOOT THROUGH PROTECTION PVCC
+ -
VSS
VREF 1.545V
1:1
x2
RBIAS OCSET VSUM DFB DROOP VO
+ -
- OCP + + - + -
V W 33%
VSEN RTN VDIFF VID0 VID1 VID2 VID3 VID4 VID DAC ISS
IDVID
SOFT
FB
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF THE ISL6263
POR VREF
DRIVER
UGATE
- SCP +
PGOOD SHORT CIRCUIT OVER CURRENT UNDER VOLTAGE OVER VOLTAGE FAULT LATCH
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FN9213.2 June 10, 2010
DRIVER
LGATE
+ + + -
PGND FDE AF_EN VW gmVin PWM
ISL6263
VW
R3 MODULATOR
+ E/A -
+ -
gmVsoft
VCOMP
COMP
VIN
ISL6263 Simplified Application Circuit for DCR Current Sensing
RVDD V5V CVDD VDD RRBIAS RBIAS CSOFT SOFT RI2UA I2UA UGATE BOOT QHS CIN VIN VIN PVCC CPVCC
CBOOT PGOOD VID<0:4> VR_ON AF_EN FDE VCC_SNS VSS_SNS VSEN RTN RS VW VSUM ISL6263 RFSET CFSET VO CN RNTCP RNTC LGATE PGND QLS PHASE
LOUT VCCGFX
COUT
RNTCS
CCOMP1 ROCSET COMP RCOMP CCOMP2 FB OCSET DFB RDRP1
VDIFF RDIFF2 CDIFF VSS RDIFF1 RGND 0 DROOP
RDRP2
CDRP
FIGURE 2. ISL6263 GPU RENDER-CORE VOLTAGE REGULATOR SOLUTION WITH DCR CURRENT SENSING
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ISL6263 Simplified Application Circuit for Resistive Current Sensing
RVDD V5V CVDD VDD RRBIAS RBIAS CSOFT SOFT RI2UA I2UA UGATE BOOT QHS CIN VIN VIN PVCC CPVCC
CBOOT PGOOD VID<0:4> VR_ON AF_EN FDE VCC_SNS VSS_SNS VSEN RTN LGATE PGND QLS PHASE
LOUT
RSNS VCCGFX
COUT
VW VSUM ISL6263 RFSET CFSET VO CN
RS
CCOMP1 ROCSET COMP RCOMP CCOMP2 FB OCSET DFB RDRP1
VDIFF RDIFF2 CDIFF VSS RDIFF1 RGND 0 DROOP
RDRP2
CDRP
FIGURE 3. ISL6263 GPU RENDER-CORE VOLTAGE REGULATOR SOLUTION WITH RESISTIVE CURRENT SENSING
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ISL6263
Absolute Voltage Ratings
VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V VSS to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V PHASE to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V (<100ns Pulse Width, 10J) -5.0V BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V BOOT to VSS or PGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V UGATE. . . . . . . . . . . . . . . . . . . (DC) -0.3V to PHASE, BOOT +0.3V (<200ns Pulse Width, 20J) -4.0V LGATE . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to PGND, PVCC +0.3V (<100ns Pulse Width, 4J) -2.0V ALL Other Pins. . . . . . . . . . . . . . . . . . . . . -0.3V to VSS, VDD +0.3V
Thermal Information
Thermal Resistance (Typical, Notes 4, 5) JA (C/W) JC (C/W) QFN Package. . . . . . . . . . . . . . . . . . . . 35 6 Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +150C Operating Temperature Range . . . . . . . . . . . . . . . .-10C to +100C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . -10C to 100C VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +25V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% FDE to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +3.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
These specifications apply for TA = -10C to +100C, unless otherwise stated. All typical specifications TA = +25C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range, -10C to +100C. SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS
PARAMETER VIN VIN Input Resistance VIN Shutdown Current VDD and PVCC VDD Input Bias Current VDD Shutdown Current VDD POR THRESHOLD Rising VDD POR Threshold Voltage Falling VDD POR Threshold Voltage REGULATION Output Voltage Range
R VIN IVIN_SHDN
VR_ON = 3.3V VR_ON = 0V, VIN = 25V
-
1.0 -
1.0
M A
IVDD IVDD_SHDN V
VR_ON = 3.3V VR_ON = 0V, VDD = 5.0V
-
2.4 -
3.0 1.0
mA A
VDD_THR VDD_THF
3.85
4.35 4.10
4.50 -
V V
V
V
GFX_MAX GFX_MIN
VID<4:0> = 00000 VID<4:0> = 11111 VID<4:0> = 00000 to 11110 (1.28750V to 0.51500V) VID<4:0> = 11110 to 11111 (0.51500V to 0.41200V)
-0.5 -1.0 -2.0
1.28750 0.41200 25.75 103 -
0.5 1.0 2.0
V V mV/step mV % % %
V VID Voltage Step
System Accuracy
VID = 1.28750V to 0.74675V TA = 0C to +100C VID = 0.72100V to 0.51500V TA = 0C to +100C VID = 0.41200 TA = 0C to +100C
PWM Nominal Frequency F
SW
RFSET = 7k, VCOMP = 2V
318
333
348
kHz
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ISL6263
Electrical Specifications
These specifications apply for TA = -10C to +100C, unless otherwise stated. All typical specifications TA = +25C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range, -10C to +100C. (Continued) SYMBOL TEST CONDITIONS MIN (Note 6) 200 TYP MAX (Note 6) 500 UNITS kHz
PARAMETER Frequency Range AMPLIFIERS Error Amplifier DC Gain (Note 8) Error Amplifier Gain-Bandwidth Product (Note 8) Error Amp Slew Rate (Note 8) FB Input Bias Current Droop Amplifier Offset RBIAS Voltage I2UA Reference Current SOFT-START CURRENT Soft-Start Current Soft Dynamic VID Current GATE DRIVER UGATE Source Resistance UGATE Source Current (Note 7) UGATE Sink Resistance UGATE Sink Current (Note 7) LGATE Source Resistance LGATE Source Current (Note 7) LGATE Sink Resistance LGATE Sink Current (Note 7) UGATE Pull-Down Resistor (Note 7) UGATE Turn-On Propagation Delay LGATE Turn-On Propagation Delay BOOTSTRAP DIODE Forward Voltage Reverse Leakage V
AV0 GBW SR IFB
DROOP_OFS
CL = 20pF CL = 20pF VFB = 1.28750V R V -0.3
RBIAS =150k
90 18 5 10 1.52 2.00
150 0.3 1.54 2.15
dB MHz V/s nA mV V A
V
RBIAS I2UA
1.50 1.85
I
I2UA = 2.5V
ISS IDVID |SOFT - REF|>100mV
-46 175
-41 200
-36 225
A A
RUGSRC IUGSRC RUGSNK IUGSNK RLGSRC ILGSRC RLGSNK ILGSNK RPD tPDRU tPDRL
500mA Source Current VUGATE_PHASE = 2.5V 500mA Sink Current VUGATE_PHASE = 2.5V 500mA Source Current VLGATE_PGND = 2.5V 500mA Sink Current VLGATE_PGND = 2.5V
-
1.0 2.0 1.0 2.0 1.0 2.0 0.5 4.0 1.1 30 15
1.5 1.5 1.5 0.9 44 30
A A A A k ns ns
PVCC = 5V, UGATE open PVCC = 5V, LGATE open
20 7
VF IR
PVCC = 5V, IF = 10mA VR = 16V
0.56 -
0.69 -
0.76 5.0
V A
POWER GOOD and PROTECTION MONITOR PGOOD Low Voltage PGOOD Leakage Current Overvoltage Threshold (VO - VSOFT) Severe Overvoltage Threshold OCSET Reference Current OCSET Voltage Threshold Offset Undervoltage Threshold (VSOFT - VO) CONTROL INPUTS VR_ON Input Low VVR_ONL 1 V VPGOOD IPGOOD VOVP VOVPS IOCSET IPGOOD = 4mA VPGOOD = 3.3V VO rising above VSOFT > 1ms VO rising above 1.55V reference > 0.5s RRBIAS = 150k -1.0 160 1.525 9.9 -3 -360 0.11 200 1.550 10.1 -300 0.40 1.0 240 1.575 10.3 3 -240 V A mV V A mV mV
VOCSET_OFS VDROOP rising above VOCSET > 120s VUVF VO falling below VSOFT for > 1ms
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ISL6263
Electrical Specifications
These specifications apply for TA = -10C to +100C, unless otherwise stated. All typical specifications TA = +25C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range, -10C to +100C. (Continued) SYMBOL VVR_ONH VAF_ENL VAF_ENH IVR_ONL IVR_ONH AF_EN Leakage IAF_ENL IAF_ENH VID<4:0> Input Low VID<4:0> Input High FDE Input Low FDE Input High VID<4:0> Leakage VVIDL VVIDH VFDEL VFDEH IVIDL IVIDH FDE Leakage IFDEL IFDEH NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Limits established by characterization and are not production tested. 8. Limits should be considered typical and are not production tested. VVID = 0V VVID = 1.0V VFDE = 0V VFDE = 1.0V VVR_ON = 0V VVR_ON = 3.3V VAF_EN = 0V VAF_EN = 3.3V TEST CONDITIONS MIN (Note 6) 2.3 2.3 -1.0 -1.0 0.7 0.7 -1.0 -1.0 TYP 0 0 0 0.45 0 0.45 0 0.45 MAX (Note 6) 1 1.0 1.0 0.3 0.3 1.0 1.0 UNITS V V V A A A A V V V V A A A A
PARAMETER VR_ON Input High AF_EN Input Low AF_EN Input High VR_ON Leakage
Functional Pin Descriptions
RBIAS (Pin 1) - Sets the internal 10A current reference. Connect a 150k 1% resistor from RBIAS to VSS. SOFT (Pin 2) - Sets the output voltage slew-rate. Connect an X5R or X7R ceramic capacitor from SOFT to VSS. The SOFT pin is the non-inverting input of the error amplifier. OCSET (Pin 3) - Sets the overcurrent threshold. Connect a resistor from OCSET to VO. VW (Pin 4) - Sets the static PWM switching frequency in continuous conduction mode. Connect a resistor from VW to COMP. COMP (Pin 5) - Connects to the output of the control loop error amplifier. FB (Pin 6) - Connects to the inverting input of the control loop error amplifier. VDIFF (Pin 7) - Connects to the output of the VDIFF differential-summing amplifier. VSEN (Pin 8) - This is the VCC_SNS input of the processor socket Kelvin connection. Connects internally to one of two non-inverting inputs of the VDIFF differential-summing amplifier. 8
RTN (Pin 9) - This is the VSS_SNS input of the processor socket Kelvin connection. Connects internally to one of two inverting inputs of the VDIFF differential-summing amplifier. DROOP (Pin 10) - Connects to the output of the droop differential amplifier and to one of two non-inverting inputs of the VDIFF differential-summing amplifier. DFB (Pin 11) - This is the feedback of the droop amplifier. Connects internally to the inverting input of the droop differential amplifier. VO (Pin 12) - Connects to one of two inverting inputs of the VDIFF differential-summing amplifier. VSUM (Pin 13) - Connects to the non-inverting input of the droop differential amplifier. VIN (Pin 14) - Connects to the R3 PWM modulator providing input voltage feed-forward. For optimum input voltage transient response, connect near the drain of the high-side MOSFETs. VSS (Pin 15) - Analog ground. VDD (Pin 16) - Input power supply for the IC. Connect to +5VDC and decouple with at least a 1F MLCC capacitor from the VDD pin to the VSS pin.
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ISL6263
BOOT (Pin 17) - Input power supply for the high-side MOSFET gate driver. Connect an MLCC bootstrap capacitor from the BOOT pin to the PHASE pin. UGATE (Pin 18) - High-side MOSFET gate driver output. Connect to the gate of the high-side MOSFET. PHASE (Pin 19) - Current return path for the UGATE highside MOSFET gate driver. Detects the polarity of the PHASE node voltage for diode emulation. Connect the PHASE pin to the drains of the low-side MOSFETs. PGND (Pin 20) - Current return path for the LGATE low-side MOSFET gate driver. The PGND pin only conducts current when LGATE pulls down. Connect the PGND pin to the sources of the low-side MOSFETs. LGATE (Pin 21) - Low-side MOSFET gate driver output. Connect to the gate of the low-side MOSFET. PVCC (Pin 22) - Input power supply for the low-side MOSFET gate driver, and the high-side MOSFET gate driver, via the internal bootstrap diode connected between the PVCC and BOOT pins. Connect to +5VDC and decouple with at least 1F of an MLCC capacitor from the PVCC pin to the PGND pin. VID0:VID4 (Pin 23:Pin 27) - Voltage identification inputs. VID0 input is the least significant bit (LSB) and VID4 input is the most significant bit (MSB). I2UA (Pin 28) - Output of an internal 2A current source. Connect a 20k resistor from the I2UA pin to the VSS pin. VR_ON (Pin 29) - A high logic signal on this pin enables the converter and a low logic signal disables the converter. AF_EN (Pin 30) - A high logic signal on this pin enables the audible frequency filter. A low logic signal on this pin disables the audible frequency filter and improves the converter efficiency. PGOOD (Pin 31) - The PGOOD pin is an open-drain output that indicates when the converter is able to supply regulated voltage. Connect the PGOOD pin to a maximum of 5V through a pull-up resistor. FDE (Pin 32) - A low logic state on this pin confines the availability of diode emulation mode to Render Suspend VID states only. A high logic state on this pin enables diode emulation for all VID states.
TABLE 1. FDE AND AF_EN STATE TABLE RENDER MODE
PERFORMANCE
FDE
0 1 0 1 0
AF_EN
0 0 1 1 0 0 1 1
PWM MODE
CCM CCM/DCM CCM CCM/DCM CCM/DCM CCM/DCM CCM/DCM CCM/DCM
VW
x x x x +33% +33% None None
AUDIO FILTER
x x x x Off Off On Off
SUSPEND
1 0 1
TABLE 2. VID TABLE FOR INTEL IMVP-6+ VCCGFX CORE VID4 x 0 0 0 0 RENDER PERFORMANCE STATES 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID3 x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 VID2 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCCGFX (V) 0 1.28750 1.26175 1.23600 1.21025 1.18450 1.15875 1.13300 1.10725 1.08150 1.05575 1.03000 1.00425 0.97850 0.95275 0.92700 0.90125 0.87550 0.84975
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TABLE 2. VID TABLE FOR INTEL IMVP-6+ VCCGFX CORE (Continued) VID4 1 1 1 RENDER SUSPEND STATES 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCCGFX (V) 0.82400V 0.79825V 0.77250V 0.74675V 0.72100V 0.69525V 0.66950V 0.64375V 0.61800V 0.59225V 0.56650V 0.54075V 0.51500V 0.41200V
VR_ON
Power-On Reset
The ISL6263 is disabled until the voltage at the VDD pin has increased above the rising VDD power-on reset (POR) VDD_THR threshold voltage. The controller will become disabled when the voltage at the VDD pin decreases below the falling POR VDD_THF threshold voltage.
Start-Up Timing
Figure 4 shows the ISL6263 start-up timing. Once VDD has ramped above VDD_THR, the controller can be enabled by pulling the VR_ON pin voltage above the input-high threshold VVR_ONH. Approximately 100s later, the soft-start capacitor CSOFT begins slewing to the designated VID set-point as it is charged by the soft-start current source ISS. The VCCGFX output voltage of the converter follows the VSOFT voltage ramp to within 10% of the VID set-point then counts 6 switching cycles, then changes the open-drain output of the PGOOD pin to high impedance. During soft-start, the regulator always operates in continuous conduction mode (CCM).
Theory of Operation
The R3 Modulator
The heart of the ISL6263 is Intersil's Robust-RippleRegulator (R3) TechnologyTM. The R3 modulator is a hybrid of fixed frequency PWM control, and variable frequency hysteretic control that will simultaneously affect the PWM switching frequency and PWM duty cycle in response to input voltage and output load transients. The term "Ripple" in the name "Robust-Ripple-Regulator" refers to the synthesized voltage-ripple signal VR that appears across the internal ripple-capacitor CR. The V R signal is a representation of the output inductor ripple current. Transconductance amplifiers measuring the input voltage of the converter and the output set-point voltage VSOFT, together produce the voltage-ripple signal VR. A voltage window signal V W is created across the VW and COMP pins by sourcing a current proportional to gmVsoft through a parallel network consisting of resistor RFSET and capacitor CFSET. The synthesized voltage-ripple signal VR along with similar companion signals are converted into PWM pulses. The PWM frequency is proportional to the difference in amplitude between V W and VCOMP. Operating on these large-amplitude, low noise synthesized signals allows the ISL6263 to achieve lower output ripple and lower phase jitter than either conventional hysteretic or fixed frequency PWM controllers. Unlike conventional hysteretic converters, the ISL6263 has an error amplifier that allows the controller to maintain tight voltage regulation accuracy throughout the VID range from 0.41200V to 1.28750V. 10
VSOFT/VCCGFX ~100s
90%
PGOOD
6 SWITCHING CYCLES
FIGURE 4. ISL6263 START-UP TIMING
Static Regulation
The VCCGFX output voltage will be regulated to the value set by the VID inputs per Table 2. A true differential amplifier connected to the VSEN and RTN pins implements processor socket Kelvin sensing for precise core voltage regulation at the GPU voltage sense points. As the load current increases from zero, the VCCGFX output voltage will droop from the VID set-point by an amount proportional to the IMVP-6+ load line. The ISL6263 can accommodate DCR current sensing or discrete resistor current sensing. The DCR current sensing uses the intrinsic series resistance of the output inductor as shown in the application circuit of Figure 2. The discrete resistor current sensing uses a shunt connected in series with the output inductor as shown in the application circuit of Figure 3. In both cases the signal is fed to the non-inverting input of the DROOP amplifier at the VSUM pin, where it is measured differentially with respect to the output voltage of the converter at the VO pin and amplified. The voltage at the
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ISL6263
DROOP pin minus the output voltage measured at the VO pin, is proportional to the total inductor current. This information is used exclusively to achieve the IMVP-6+ load line as well as the overcurrent protection. It is important to note that this current measurement should not be confused with the synthetic current ripple information created within the R3 modulator. When using inductor DCR current sensing, an NTC element is used to compensate the positive temperature coefficient of the copper winding thus maintaining the load-line accuracy. sensing allows the voltage regulator to tightly control the processor voltage at the die, compensating for various resistive voltage drops in the power delivery path. Since the voltage feedback is sensed at the processor die, removing the GPU will open the voltage feedback path of the regulator, causing the output voltage to rise towards VIN. The ISL6263 will shut down when the voltage between the VO and VSS pins exceeds the severe overvoltage protection threshold VOVPS of 1.55V. To prevent this issue from occurring, it is recommended to install resistors Ropn1 and Ropn2 as shown in Figure 5. These resistors provide voltage feedback from the regulator local output in the absence of the GPU. These resistors should be in the range of 20 to 100.
Processor Socket Kelvin Voltage Sensing
The remote voltage sense input pins VSEN and RTN of the ISL6263 are to be terminated at the die of the GPU through connections that mate at the processor socket. (The signal names are Vcc_sense and Vss_sense respectively.) Kelvin
VDD 10A - OCP + + DROOP -
LOUT ROCSET PHASE RS
DCR
OCSET VSUM
COUT ESR
+ - + + + - VDIFF
DROOP CN VO CDRP RDRP2
RNTCS RDRP1 RNTC RNTCP
DFB
VSEN RTN
CFILTER1
RFILTER1 RFILTER2
ROPN1
VCC_SNS VSS_SNS ROPN2
To Processor Socket Kelvin Connections
CFILTER2
CFILTER3
FIGURE 5. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH GPU SOCKET KELVIN SENSING AND INDUCTOR DCR CURRENT SENSING
High Efficiency Diode Emulation Mode
The ISL6263 operates in continuous-conduction-mode (CCM) during heavy load for minimum conduction loss by forcing the low-side MOSFET to operate as a synchronous rectifier. Depending upon the VID and FDE pin states, an improvement in light-load efficiency can be achieved by operating in discontinuous-conduction-mode (DCM) where the low-side MOSFET is operated in diode-emulation-mode (DEM), forcing the low-side MOSFET to block negative inductor current flow. Positive-going inductor current flows from either the source of the high-side MOSFET, or the drain of the low-side MOSFET. Negative-going inductor current flows into the 11
source of the high-side MOSFET, or the drain of the low-side MOSFET. When the low-side MOSFET conducts positive inductor current, the phase voltage will be negative with respect to the VSS pin. Conversely, when the low-side MOSFET conducts negative inductor current, the phase voltage will be positive with respect to the VSS pin. Negative inductor current occurs in CCM when the output load current is less than 1/2 the inductor ripple current. Sinking negative inductor through the low-side MOSFET lowers efficiency through unnecessary conduction losses. Upon entering DEM the PWM switching frequency is automatically shifted downward by an increase of the window voltage V W of 33%. The PWM switching frequency will continue to decrease as the load continues to decrease. The reduction of PWM
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frequency further improves efficiency by reducing switching losses. The converter will automatically enter DEM after eight consecutive PWM pulses where the PHASE pin has detected positive voltage shortly after the LGATE pin has gone high. The converter will return to CCM on the following cycle after the PHASE pin detects negative voltage shortly after the LGATE pin has gone high, indicating that the body diode of the low-side MOSFET is conducting positive inductor current. The converter inhibits the automatic 33% change of V W whenever the audio filter is enabled. Smooth mode transitions are facilitated by the R3 modulator which correctly maintains the internally synthesized ripple current information throughout mode transitions. MOSFET body diode. The controller will remain latched in the fault state until the VR_ON pin has been pulled below the falling VR_ON threshold voltage VVR_ONL or until VDD has gone below the falling POR threshold voltage VVDD_THF. A severe-overvoltage protection fault occurs immediately after the voltage between the VO and VSS pins exceed the rising severe-overvoltage threshold VOVPS which is 1.545V, the same reference voltage used by the VID DAC. The ISL6263 will latch UGATE and PGOOD low but unlike other protective faults, LGATE remains high until the voltage between VO and VSS falls below approximately 0.77V, at which time LGATE is pulled low. The LGATE pin will continue to switch high and low at 1.545V and 0.77V until VDD has gone below the falling POR threshold voltage VVDD_THF. This provides maximum protection against a shorted highside MOSFET while preventing the output voltage from ringing below ground. The severe-overvoltage fault circuit can be triggered after another fault has already been latched.
TABLE 3. FAULT PROTECTION SUMMARY OF ISL6263 FAULT DURATION PRIOR TO PROTECTION 120s
Protection
The ISL6263 provides overcurrent protection (OCP), overvoltage protection (OVP), and undervoltage protection (UVP) as shown in Table 3. Overcurrent protection is tied to the voltage droop, which is determined by the resistors selected in the Static Droop Design Using DCR Sensing section. After the load line is set, the OCSET resistor can be selected. The OCP threshold detector is checked every 15s and will increment a counter if the OCP threshold is exceeded, conversely the counter will be decremented if the load current is below the OCP threshold. The counter will latch an OCP fault when the counter reaches eight. The fastest OCP response for overcurrent events occurring above the OCP threshold but below twice the OCP threshold is 120s, which is eight counts at 15s each. The ISL6263 will latch an OCP fault within 2s for an overcurrent exceeding twice the OCP threshold to maximize protection against hard shorts. The value of ROCSET is calculated as Equation 1:
I OC R droop R OCSET = --------------------------------10A (EQ. 1)
FAULT TYPE Overcurrent
PROTECTION ACTIONS
FAULT RESET
LGATE, UGATE, and Cycle PGOOD latched low VR_ON or VDD LGATE, UGATE, and Cycle PGOOD latched low VR_ON or VDD LGATE, UGATE, and Cycle PGOOD latched low VR_ON or VDD Cycle UGATE, and PGOOD latched low, VDD only LGATE toggles ON when VO>1.55V OFF when VO <0.77V until fault reset LGATE, UGATE, and Cycle PGOOD latched low VR_ON or VDD
Short Circuit
<2s
Overvoltage (+200mV) between VO pin and SOFT pin Severe Overvoltage (+1.55V) between VO pin and VSS pin
1ms
Immediately
For example: The desired overcurrent trip level, Ioc, is 30A, Rdroop load-line is 8m, Equation 1 gives ROCSET = 24k. Undervoltage protection is independent of the overcurrent protection. If the output voltage measured on the VO pin is less than +300mV below the voltage on the SOFT pin for longer than 1ms, the controller will latch a UVP fault. If the output voltage measured on the VO pin is greater than +200mV above the voltage on the SOFT pin for longer than 1ms, the controller will latch an OVP fault. Keep in mind that VSOFT will equal the voltage level commanded by the VID states only after the soft-start capacitor CSOFT has slewed to the VID DAC output voltage. The UVP and OVP detection circuits act on static and dynamic VSOFT voltage. When an OCP, OVP, or UVP fault has been latched, PGOOD becomes a low impedance and the gate driver outputs UGATE and LGATE are pulled low. The energy stored in the inductor is dissipated as current flows through the low-side
Undervoltage (-300mV) between VO pin and SOFT pin
1ms
Gate-Driver Outputs LGATE and UGATE
The ISL6263 has internal high-side and low-side N-Channel MOSFET gate-drivers. The LGATE driver is optimized for low duty-cycle applications where the low-side MOSFET conduction losses are dominant. The LGATE pull-down resistance is very low in order to clamp the gate-source voltage of the MOSFET below the VGS(th) at turnoff. The current transient through the low-side gate at turnoff can be considerable due to the characteristic large switching charge of a low r DS(on) MOSFET.
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ISL6263
Adaptive shoot-through protection prevents the gate-driver outputs from going high until the opposite gate-driver output has fallen below approximately 1V. The UGATE turn-on propagation delay tPDRU and LGATE turn-on propagation delay tPDRL are found in the Electrical Specifications table. The power for the LGATE gate-driver is sourced directly from the PVCC pin. The power for the UGATE gate-driver is sourced from a boot-strap capacitor connected across the BOOT and PHASE pins. The boot capacitor is charged from PVCC through an internal boot-strap diode each time the low-side MOSFET turns on, pulling the PHASE pin low. where QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET. The VBOOT term is defined as the allowable droop in the rail of the upper drive. As an example, suppose an upper MOSFET has a gate charge, QGATE , of 25nC at 5V and also assume the droop in the drive voltage at the end of a PWM cycle is 200mV. One will find that a bootstrap capacitance of at least 0.125F is required. The next larger standard value capacitance is 0.15F. A good quality ceramic capacitor is recommended.
Soft-Start and Soft Dynamic VID Slew Rates
The output voltage of the converter tracks VSOFT, the voltage across the SOFT and VSS pins. Shown in Figure 1, the SOFT pin is connected to the output of the VID DAC through the unidirectional soft-start current source ISS or the bidirectional soft-dynamic VID current source IDVID, and the non-inverting input of the error amplifier. Current is sourced from the SOFT pin when ISS is active. The SOFT pin can both source and sink current when IDVID is active. The soft-start capacitor CSOFT changes voltage at a rate proportional to ISS or IDVID. The ISL6263 automatically selects ISS for the soft-start sequence so that the inrush current through the output capacitors is maintained below the OCP threshold. Once soft-start has completed, IDVID is automatically selected for output voltage changes commanded by the VID inputs, charging CSOFT when the output voltage is commanded to rise, and discharging CSOFT when the output voltage is commanded to fall. The IMVP-6+ Render Voltage Regulator specification requires a minimum of 10mV/s for SLEWRATEGFX. The value for CSOFT must guarantee the minimum slew-rate of 10mV/s when the soft-dynamic VID current source I DVID is the minimum specified value in the Electrical Specifications table. The value of CSOFT, can be calculated from Equation 3:
I DVIDmin 175A C SOFT = ------------------------ = ----------------- = 0.0175F 10K 10mV --------------- s (EQ. 3)
PWM
LGATE 1V
UGATE 1V
t PDRU
t PDRL
FIGURE 6. GATE DRIVER TIMING DIAGRAM
Internal Bootstrap Diode
The ISL6263 has an integrated boot-strap Schottky diode connected from the PVCC pin to the BOOT pin. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit.
2.0 1.8 1.6 CBOOT_CAP (F) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 20nC 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VBOOT_CAP (V) 0.8 0.9 1.0 QGATE = 100nC
nC 50
0.0 0.0
Choosing the next lower standard component value of 0.015F will guarantee 10mV/s SLEWRATEGFX. This choice of CSOFT controls the startup slew-rate as well. One should expect the output voltage during soft-start to slew to the voltage commanded by the VID settings at a nominal rate given by Equation 4:
I SS dV SOFT 41A 2.8mV ---------------------- = ------------------ = ---------------------- ----------------dt C SOFT 0.015F s (EQ. 4)
FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
The minimum value of the bootstrap capacitor can be calculated from Equation 2:
Q GATE C BOOT ----------------------V BOOT (EQ. 2)
Note that the slewrate is the average rate of change between the initial and final voltage values. The slewrate is moderated as VCCGFX approaches the voltage commanded by the VID inputs.
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RBIAS Current Reference
The RBIAS pin is internally connected to a 1.545V reference through a 3k resistance. A bias current is established by connecting a 1% tolerance, 150k resistor between the RBIAS and VSS pins. This bias current is mirrored, creating the OCSET reference current I OCSET that is sourced from the OCSET pin. Do not connect any other components to this pin, as they will have a negative impact on the performance of the IC. shows the DCR sensing method. Figure 8 shows the simplified model of the droop circuitry. The inductor DC current generates a DC voltage drop on the inductor DCR. Equation 7 gives this relationship:
V DCR = I o DCR (EQ. 7)
I2UA Current Reference
The I2UA pin is connected to a 2A current source II2UA. This current source is made available for implementing a voltage offset of the commanded VID states. A 20k resistor RI2UA should be connected across the I2UA and VSS pins if the II2UA current source is unused.
An R-C network senses the voltage across the inductor to get the inductor current information. RNTCEQ represents the NTC network consisting of RNTC, RNTCS, and RNTCP. The choice of RS will be discussed in the next section. The first step in droop load line compensation is to adjust RNTCEQ, and RS such that the correct droop voltage appears even at light loads between the VSUM and VO pins. As a rule of thumb, the voltage drop VN across the RNTCEQ network, is set to be 0.5x to 0.8x VDCR. This gain, defined as G1, provides a reasonable amount of light load signal from which to derive the droop voltage. The NTC network resistor value is dependent on temperature and is given by Equation 8:
( R NTC + R NTCS ) R NTCP R N ( T ) = ----------------------------------------------------------------------R NTC + R NTCS + R NTCP (EQ. 8)
Setting the PWM Switching Frequency
The R3 modulator scheme is not a fixed-frequency architecture, lacking a fixed-frequency clock signal to produce PWM. The switching frequency increases during the application of a load to improve transient performance. The static PWM frequency varies slightly depending on the input voltage, output voltage, and output current, but this variation is normally less than 10% in continuous conduction mode. Refer to Figure 2, and find that resistor R FSET is connected between the V W and COMP pins. A current is sourced from VW through RFSET creating the synthetic ripple window voltage signal V W which determines the PWM switching frequency. The relationship between the resistance of RFSET and the switching frequency in CCM is approximately given by Equation 5:
1 R FSET = ----------------------------------------------------6 ( T - 0.29 x10 ) 47 (EQ. 5)
G1, the gain of VN to VDCR, is also dependent on the temperature of the NTC thermistor:
RN ( T ) G 1 ( T ) = ------------------------------RN ( T ) + RS (EQ. 9)
The inductor DCR is a function of temperature and is approximately given by Equation 10:
DCR ( T ) = DCR 25C ( 1 + 0.00393 ( T - 25C ) ) (EQ. 10)
The droop amplifier output voltage divided by the total load current is given by Equation 11:
R droop = G 1 ( T ) DCR 25C ( 1 + 0.00393 ( T - 25C ) ) k droopamp (EQ. 11)
For example, the value of RFSET for 300kHz operation is approximately:
3 1 7 x10 = ---------------------------------------------------------------------------6 -6 ( 3.33 x10 - 0.29 x10 ) 47
(EQ. 6)
This relationship only applies to operation in constant conduction mode because the PWM frequency naturally decreases as the load decreases while in diode emulation mode. Note that the Electrical Specifications table gives the nominal PWM frequency of 333kHz with RFSET = 7k, different from the result of equation Equation 6. This is because the IC is trimmed with VCOMP = 2V which is higher than the typical value encountered in a typical application.
Rdroop is the actual load line slope, and 0.00393 is the temperature coefficient of the copper. To make Rdroop independent of the inductor temperature, it is desired to have Equation 12:
G 1 ( T ) ( 1 + 0.00393 ( T - 25C ) ) G 1t arg et (EQ. 12)
where G1target is the desired ratio of Vn / VDCR. Therefore, the temperature characteristics G1 is described by Equation 13:
G 1t arg et G 1 ( T ) = -------------------------------------------------------------------( 1 + 0.00393 ( T - 25C ) ) (EQ. 13)
Static Droop Design Using DCR Sensing
The ISL6263 has an internal differential amplifier to accurately regulate the voltage at the processor die. For DCR sensing, the process to compensate the DCR resistance variation takes several iterative steps. Figure 2
It is recommended to begin your droop design using the RNTC, RNTCS, and RNTCP component values of the evaluation board available from Intersil.
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The gain of the droop amplifier circuit is Equation 14:
R DRP2 k droopamp = 1 + ------------------R DRP1 (EQ. 14)
Rdroop is 8m per Intel IMVP-6+ specification and RDRP1 is typically 1k. The effectiveness of the RNTCEQ network is sensitive to the coupling coefficient between the NTC thermistor and the inductor. The NTC thermistor should be placed in the closet proximity of the inductor.
After determining RS and RNTCEQ networks, use Equation 15 to calculate the droop resistances RDRP1 and RDRP2.
R droop R DRP2 = ------------------------------------------ - 1 R DRP1 DCR G 1 ( 25C ) (EQ. 15)
VDD 10A - OCP + + DROOP -
OCSET VSUM DFB DROOP
ROCSET RS
-
FIGURE 8. EQUIVALENT MODEL FOR DROOP CIRCUIT USING INDUCTOR DCR CURRENT SENSING
VDD 10A - OCP + + DROOP -
OCSET VSUM DFB DROOP
ROCSET RS
+ -
FIGURE 9. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DISCRETE RESISTOR CURRENT SENSING
15
RDRP1
CN
VO
RDRP2
RDRP1
CN
VO
RNTCEQ
+
RDRP2
VDCR
VRSNS
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To see whether the NTC network successfully compensates the DCR change over temperature, one can apply full load current and wait for the thermal steady state and see how much the output voltage deviates from the initial voltage reading. A good compensation can limit the drift to less than 2mV. If the output voltage is decreasing when the temperature increases, that ratio between the NTC thermistor value and the rest of the resistor divider network has to be increased. Following the evaluation board value and layout of NTC placement will minimize the engineering time. The current sensing traces should be routed directly to the inductor pads for accurate DCR voltage drop measurement. However, due to layout imperfection, the calculated RDRP2 may still need slight adjustment to achieve optimum load line slope. It is recommended to adjust RDRP2 after the system has achieved thermal equilibrium at full load. For example, if the maximum load current is 20A, one should apply a 20A load current and look for 160mV output voltage droop. If the voltage droop is 155mV, the new value of RDRP2 is calculated by Equation 16:
160mV R DRP2new = ------------------- ( R DRP1 - R DPR2 ) - R DRP1 155mV (EQ. 16)
icore Vcore
Icore Vcore
Vcore
Vcore= IcorexRdroop
FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
icore Vcore
Vcore
FIGURE 11. LOAD TRANSIENT RESPONSE WHEN CN IS TOO SMALL
For the best accuracy, the effective resistance on the DFB and VSUM pins should be identical so that the bias current of the droop amplifier does not cause an offset voltage.
icore Vcore
Dynamic Droop Capacitor Design Using DCR Sensing
Figure 10 shows the desired waveforms during load transient response. VCCGFX needs to follow the change in Icore as close as possible. The transient response of VCCGFX is determined by several factors, namely the choice of output inductor, output capacitor, compensator design, and the design of droop capacitor CN. If CN is designed correctly, the voltage VDROOP -VO will be an excellent representation of the inductor current. Given the correct CN design, VCCGFX has the best chance of tracking ICORE, if not, its voltage will be distorted from the actual waveform of the inductor current and worsens the transient response. Figure 11 shows the transient response when CN is too small allowing VCCGFX to sag excessively during the load transient. Figure 12 shows the transient response when CN is too large. VCCGFX takes too long to droop to its final value.
Vcore
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN CN IS TOO LARGE
The current sensing network consists of RNTCEQ, RS, and CN. The effective resistance is the parallel of RNTCEQ and RS. The RC time constant of the current sensing network needs to match the L/DCR time constant of the inductor to get the correct representation of the inductor current waveform. Equation 17 shows this relationship:
R NTCEQ R S L ------------- = -------------------------------------- C N DCR R NTCEQ + R S (EQ. 17)
Solution of CN yields Equation 18:
L ------------- DCR C N = ------------------------------------------ R NTCEQ R S -------------------------------------- R NTCEQ + R S (EQ. 18)
For example: L = 0.45H, DCR = 1.1m, RS = 7.68k, and RNTCEQ = 3.4k:
0.45H ------------------- 1.1m C N = ------------------------------------------------ = 174nF 3.4k 7.68k ------------------------------------------ 3.4k + 7.68k (EQ. 19)
Since the inductance and the DCR typically have 20% and 7% tolerance respectively, CN needs to be fine tuned on the 16
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actual board by examining the transient voltage. It is recommended to choose the minimum capacitance based on the maximum inductance. CN also needs to be a highgrade capacitor such as NPO/COG or X7R with tight tolerance. The NPO/COG caps are only available in small capacitance values. In order to use such capacitors, the resistors and thermistors surrounding the droop voltage sensing and droop amplifier need to be scaled up 10x to reduce the capacitance by 10x. calculate the compensator parameters. Caution needs to be used in choosing the input resistor to the FB pin. Excessively high resistance will cause an error to the output voltage regulation due to the bias current flowing through the FB pin. It is recommended to keep this resistor below 3k.
Layout Considerations
As a general rule, power should be on the bottom layer of the PCB and weak analog or logic signals are on the top layer of the PCB. The ground-plane layer should be adjacent to the top layer to provide shielding.
Static and Dynamic Droop using Discrete Resistor Sensing
Figure 3 shows a detailed schematic using discrete resistor sensing of the inductor current. Figure 9 shows the equivalent circuit. Since the current sensing resistor voltage represents the actual inductor current information, RS and CN simply provide noise filtering. A low ESL sensing resistor is strongly recommended for RSNS because this parameter is the most significant source of noise that affects discrete resistor sensing. It is recommended to start out using 100 for RS and 47pF for CN. Since the current sensing resistance changes very little with temperature, the NTC network is not needed for thermal compensation. Discrete resistor sensing droop design follows the same approach as DCR sensing. The voltage on the current sensing resistor is given by Equation 20:
V RSNS = I o R SNS (EQ. 20)
Inductor Current Sensing and the NTC Placement
It is crucial that the inductor current be sensed directly at the PCB pads of the sense element, be it DCR sensed or discrete resistor sensed. The effect of the NTC on the inductor DCR thermal drift is directly proportional to its thermal coupling with the inductor and thus, the physical proximity to it.
Signal Ground and Power Ground
The ground plane layer should have a single point connection to the analog ground at the VSS pin. The VSS island should be located under the IC package along with the weak analog traces and components. The paddle on the bottom of the ISL6263 QFN package is not electrically connected to the IC however, it is recommended to make a good thermal connection to the VSS island using several vias. Connect the input capacitors, the output capacitors, and the source of the lower MOSFETs to the power ground plane.
Equation 21 shows the droop amplifier gain. So the actual droop is given by:
R DRP2 R droop = R SNS 1 + ------------------ R DRP1 (EQ. 21)
LGATE, PVCC, and PGND
PGND is the return path for the pull-down of the LGATE low-side MOSFET gate driver. Ideally, PGND should be connected to the source of the low-side MOSFET with a low-resistance, low-inductance path. The LGATE trace should be routed in parallel with the trace from the PGND pin. These two traces should be short, wide, and away from other traces because of the high peak current and extremely fast dv/dt. PVCC should be decoupled to PGND with a ceramic capacitor physically located as close as practical to the IC pins.
VIAS TO GROUND PLANE GND OUTPUT CAPACITORS SCHOTTKY DIODE LOW-SIDE MOSFETS INPUT CAPACITORS
Solution to RDRP2 yields Equation 22:
R droop R DRP2 = R DRP1 ------------------ - 1 R SNS (EQ. 22)
For example: Rdroop = 8.0m, RSNS = 1.0m, and RDRP1 = 1k, RDRP2 then = 7k. The current sensing traces should be routed directly to the current sensing resistor pads for accurate measurement. However, due to layout imperfection, the calculated RDRP2 may still need slight adjustment to achieve optimum load line slope. It is recommended to adjust RDRP2 after the system has achieved thermal equilibrium at full load.
VOUT INDUCTOR HIGH-SIDE MOSFETS PHASE NODE
Dynamic Mode of Operation - Compensation Parameters
The voltage regulator is equivalent to a voltage source in series with the output impedance. The voltage source is the VID state and the output impedance is 8.0m in order to achieve the 8.0mV/A load line. It is highly recommended to design the compensation such that the regulator output impedance is 8.0m. Intersil provides a spreadsheet to
VIN
FIGURE 13. TYPICAL POWER COMPONENT PLACEMENT
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UGATE, BOOT, and PHASE
PHASE is the return path for the entire UGATE high-side MOSFET gate driver. The layout for these signals require similar treatment, but to a greater extent, than those for LGATE, PVCC, and PGND. These signals swing from approximately VIN to VSS and are more likely to couple into other signals.
SOFT, OCSET, V W, COMP, FB, VDIFF, DROOP, DFB, VO, and VSUM
The traces and components associated with these pins require close proximity to the IC as well as close proximity to each other. This section of the converter circuit needs to be located above the island of analog ground with the single-point connection to the VSS pin.
VSEN and RTN
These traces should be laid out as noise sensitive. For optimum load line regulation performance, the traces connecting these two pins to the Kelvin sense leads of the processor should be laid out away from rapidly rising voltage nodes, (switching nodes) and other noisy traces. The filter capacitors CFILTER1, CFILTER2, and CFILTER3 used in conjunction with filter resistors RFILTER1 and RFILTER2 form common mode and differential mode filters as shown in Figure 8. The noise environment of the application and actual board layout conditions will drive the extent of filter complexity. The maximum recommended resistance for RFILTER1 and RFILTER2 is approximately 10 to avoid interaction with the 50k input resistance of the remote sense differential amplifier. The physical location of these resistors is not as critical as the filter capacitors. Typical capacitance values for CFILTER1, CFILTER2, and CFILTER3 range between 330pF to 1000pF and should be placed near the IC.
Resistor RS
Resistor RS is preferably located near the boundary between the power ground and the island of analog ground connected to the VSS pin.
VID<0:4>, AF_EN, PGOOD, and VR_ON
These are logic signals that do not require special attention.
FDE
This logic signal should be treated as noise sensitive and should be routed away from rapidly rising voltage nodes, (switching nodes) and other noisy traces.
VIN
The VIN signal should be connected near the drain of the high-side MOSFET.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. It is best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application. An MLCC should be connected directly across the drain of the high-side MOSFET and the source of the low-side MOSFET to suppress turn-off voltage spikes.
RBIAS and I2UA
The resistors RRBIAS and RI2UA should be placed in close proximity to the ISL6263 using a noise-free current return path to the VSS pin.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18
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Package Outline Drawing
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 4/10
4X 3.5 5.00 A B 6 PIN 1 INDEX AREA 28X 0.50 6 PIN #1 INDEX AREA
25 24
32 1
5.00
3 .10 0 . 15
17
(4X) 0.15 16 9
8
0.10 M C A B 4 32X 0.23 - 0.05
+ 0.07
32X 0.40 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0.1
C
BASE PLANE
SEATING PLANE 0.08 C
( 4. 80 TYP ) ( 3. 10 )
( 28X 0 . 5 )
SIDE VIEW
(32X 0 . 23 )
C ( 32X 0 . 60)
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
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